In advanced technologies (e.g., 0.13 μm process and below), noise can greatly affect the write voltage trip point (e.g., the voltage on a bit line sufficient to write data to a node) of a static random access memory (SRAM), specifically in lower operation voltages (e.g., lower voltage VCC at 0.65 V versus nominal voltage VCC at 0.85 V). The noise limits the range of the SRAM operation voltage and increases power consumption because the SRAM needs to use a higher supply voltage VCC. To improve the situation, in one approach, a bit line having a negative voltage is used in a write operation. This approach, however, has various drawbacks. For example, a voltage pump circuit is required to provide the negative voltage. The voltage pump mechanism is usually not power efficient. Controlling the voltage level of a negative voltage is not easy. A potential risk exists because of the forward bias that can cause a current leak from the bit line to the substrate of the transistors in the memory, which requires a careful handling and causes difficulty in using the SRAM in a compiler.
Like reference symbols in the various drawings indicate like elements.